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Arumugam, N.
- A Trivial Scheme for Detecting and Preventing Unauthorized Access of Resources on a Network Domain
Abstract Views :178 |
PDF Views:3
Authors
N. Arumugam
1,
C. Venkatesh
2
Affiliations
1 Anna University of Technology, Coimbatore, Tamilnadu, IN
2 EBET Group of Institutions, Kankayam, Tamilnadu, IN
1 Anna University of Technology, Coimbatore, Tamilnadu, IN
2 EBET Group of Institutions, Kankayam, Tamilnadu, IN
Source
Networking and Communication Engineering, Vol 3, No 2 (2011), Pagination: 132-135Abstract
The significant success and growth of Internet is that any application can send anything to any one any time, without needing to obtain advance permission from network administrators. This openness of the internet architecture leads to unauthorized access. Defending against these types of illicit access is the hardest security problems on the internet. To solve this problem, the proposed light weight scheme to detect and prevent the unauthorized request, instead of being able to send anything to anyone at the time, the sender must obtain the endorsement secret key or secret code from the destination server. To validate the legitimate of the request, a network Authentication Server (AS) performs an authentication process for each initiating host. The simulation result proves its effectiveness for preventing unauthorized access on network resource.Keywords
IP Spoofing, Key Distribution, Authentication Process.
- MQARR-AODV: A Novel Multipath QOS Aware Reliable Reverse On-Demand Distance Vector Routing Protocol for Mobile AD-HOC Networks
Abstract Views :167 |
PDF Views:0
Authors
Affiliations
1 Department of Computer Science, Mother Teresa Women University, GD
2 Department of Computer Science, Mother Teresa Women University, IN
1 Department of Computer Science, Mother Teresa Women University, GD
2 Department of Computer Science, Mother Teresa Women University, IN
Source
ICTACT Journal on Communication Technology, Vol 3, No 4 (2012), Pagination: 634-638Abstract
MANET (Mobile Ad-hoc Network) is an infra structure less wireless ad-hoc network that does not require any basic central control. The topology of the network changes drastically due to very fast mobility of nodes. So an adaptive routing protocol is needed for routing in MANET. AODV (Ad-hoc On-demand Distance Vector) routing is the effective and prominent on-demand Ad-hoc routing protocols. During route establishment phase in traditional AODV, only one route reply message will be sent in the reverse path to establish routing path. The high mobility of nodes may affect the reply messages which lead to the retransmission of route request message by the sender which in turn leads to higher communication delay, power consumption and the reduction in the ratio of packets delivered. Sending multiple route reply messages and establishing multiple paths in a single path discovery will reduce the routing overhead involved in maintaining the connection between source and destination nodes. Multipath routing can render high scalability, end-to-end throughput and provide load balancing in MANET. The new proposed novel Multipath QoS aware reliable routing protocol establishes two routes of maximum node disjoint paths and the data transfer is carried out in the two paths simultaneously. To select best paths, the new proposed protocol uses three parameters Link Eminence, MAC overhead and node residual energy. The experimental values prove that the MQARR-AODV protocol achieves high reliability, stability, low latency and outperforms AODV by the less energy consumption, overhead and delay.Keywords
MANET, AODV, Reverse AODV, Multipath, Quality of Service.- Drain Current Characteristics of Silicon Nanowire Field Effect Transistor
Abstract Views :179 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, IN
1 Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, IN
Source
ICTACT Journal on Microelectronics, Vol 2, No 3 (2016), Pagination: 284-287Abstract
This paper presents the simulation study of characteristics of an 11nm Silicon Nanowire Field Effect Transistor. This architecture is applicable for ultra-scaled devices up to sub-11 nm technology nodes that employ silicon films of a few nm in thickness. The defining characteristics of ultrathin silicon devices such as Short Channel Effects and Quasi-Ballistic transport are considered in modelling the device. Device geometries play a very important role in short channel devices, and hence their impact on drain current is also analyzed by varying the silicon and oxide thickness. The proposed simulation model gives a detailed outlook on the characteristics of the nanowire device in the inversion regime.Keywords
Nanowire Transistors, Drain Current Characteristics.- Design of Adiabatic Logic Based Comparator for Low Power and High Speed Applications
Abstract Views :201 |
PDF Views:1
Authors
Affiliations
1 Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, IN
2 Department of Electronics and Communication Engineering, Dr. Sivanthi Aditanar College of Engineering, IN
1 Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, IN
2 Department of Electronics and Communication Engineering, Dr. Sivanthi Aditanar College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 1 (2017), Pagination: 365-369Abstract
This paper presents a novel modified comparator based on the combination of 2N-2N2P adiabatic logic and two phase adiabatic static clocked logic (2N-2N2P and 2PASCL), combination of efficient charge recovery adiabatic logic and two phase adiabatic static clocked logic (ECRL and 2PASCL). This new structure computes a decision making signal faster than the existing methods. The introduced logic based comparator demonstrates that the usage of high speed decision making signal allows high speed comparator, saving 60-80% of power in comparison with existing renowned conventional comparators. Adiabatic logic based circuit carry out less power consumption by constraining current flowing through devices with less voltage drop and by reusing the energy stored at output node instead of discharging it to ground. The design is simulated using Cadence Virtuoso Environment.Keywords
Adiabatic Logic, ECRL, 2PASCL, 2N-2N2P, Comparator.References
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- Design and Analysis of InP and GaAs Double Gate MOSFET Transistors for Low Power Applications
Abstract Views :134 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, National Engineering College, IN
2 Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, IN
1 Department of Electronics and Communication Engineering, National Engineering College, IN
2 Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, IN